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[ARM-PowerPC-ColdFire-MIPS] ethernet_verilog

Description: 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
Platform: | Size: 78848 | Author: 张念华 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 硬件设计vhdl_cpu1,1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below.-hardware design vhdl_cpu1, 1. You may copy and distribute verbatim copies of this core, as long-- as this file, and the other associated files, remain intact and-- unmodified. Modifications are outlined below.
Platform: | Size: 1024 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] RISC8.ZIP

Description: 简单的一个8位RISC，Verilog HDL代码,类型为pic16c57-a simple eight RISC, Verilog HDL code, the type of pic16c57
Platform: | Size: 80896 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] 数字系统设计教程4_9

Description: vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
Platform: | Size: 244736 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] 数字系统设计相关

Description: 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
Platform: | Size: 45056 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] tbcpu8bit2

Description: 极小的CPU的VHDL源代码，仅需要占用32个宏单元的CPLD。除了VHDL源代码还包括了汇编器的C源代码-minimal CPU VHDL source code, only occupy 32 macrocell CPLD. Apart from VHDL source code also includes a compilation of C source code
Platform: | Size: 205824 | Author: 冰激凌 | Hits:

[Other] vhdl实例-完整微处理器系统模型

Description: vhdl实例-完整微处理器（cpu）系统模型 -VHDL-integrity microprocessor (CPU) system model
Platform: | Size: 2048 | Author: 张洪 | Hits:

[VHDL-FPGA-Verilog] RISC

Description: hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
Platform: | Size: 128000 | Author: 12 | Hits:

[VHDL-FPGA-Verilog] vhdl_8cpu

Description: VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code
Platform: | Size: 52224 | Author: 紫蓝 | Hits:

[MiddleWare] cpu_intf

Description: cpu的VHDL的源代码，功能的简单实现-cpu VHDL source code, the function of a simple realization
Platform: | Size: 1024 | Author: 陈娟娟 | Hits:

[VHDL-FPGA-Verilog] vhdlfinishcpu

Description: 用vhdl实现简单cpu的功能,能够很好的帮助特别是初学者学习vhdl的功能!-with vhdl cpu to achieve simple function can be very helpful, especially beginners learning vhdl function!
Platform: | Size: 53248 | Author: 敖鱼 | Hits:

[Software Engineering] cpu-16-vhdl

Description: 16位cpu的vhdl源代码。 自己看看，没有注释。-16 cpu vhdl the source code. See for yourself, not Notes.
Platform: | Size: 95232 | Author: 童宗挺 | Hits:

[Other] CPU8

Description: 本源码实现了8为cpu，开发语言为vhdl，里面有详细的文档和vhdl工程源码-the source to achieve the 8 cpu, development language for vhdl. There are detailed documentation and source code works vhdl
Platform: | Size: 732160 | Author: digg | Hits:

[MPI] sdgshjd

Description: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar]- 4 division of vhdl source [vh dl example. rar]- highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
Platform: | Size: 1024 | Author: 张瑞 | Hits:

[VHDL-FPGA-Verilog] CPU2

Description: 利用VHDL编写的简单CPU程序，能进行简单的加减运算，有运算结果截图的-VHDL prepared using simple procedures CPU can perform simple addition and subtraction calculations, the results have a screenshot of computing
Platform: | Size: 53248 | Author: 张娟 | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter10

Description: 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Platform: | Size: 6872064 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 用Verilog HDL语言写一个简单的处理器CPU。包括IR,Control unit,A,Addsub,G,Counter,8个寄存器。-Verilog HDL language used to write a simple processor CPU. Including IR, Control unit, A, Addsub, G, Counter, 8 registers.
Platform: | Size: 1190912 | Author: sunying | Hits:

[VHDL-FPGA-Verilog] Project-8

Description: 课程设计时用verilogHDL写的MIPS CPU-MIPS CPU coded with Verilog HDL
Platform: | Size: 790528 | Author: 高炼 | Hits:
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